This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of static random access memories (SRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT of cell 2 of FIG. 1, if bit line BLTk is unable to sufficiently discharge storage node SNT to a sufficient level to trip the inverters, cell 2 may not latch to the desired data state.
Cell stability failures are the converse of write failures—while a write failure occurs if a cell is too stubborn in changing its state, a cell stability failure occurs if a cell changes its state too easily. Noise of sufficient magnitude coupling to the bit lines of unselected cells, for example during a write to a selected memory cell in the same row, can cause a false write of data to unselected cells in that same row. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the unselected cells (i.e., the “half-selected” cells in unselected columns of the selected row). The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.
As known in the art, an important measure of the functionality of an SRAM memory cell is the minimum power supply voltage (i.e., the differential voltage between array power supply voltage Vdda and array reference voltage Vssa in the arrangement of FIG. 1) at which that memory cell can be successfully written and read. It is desirable that this minimum power supply voltage be as low as possible, particularly for memories to be implemented in portable and other battery-powered or otherwise power-sensitive applications. This minimum power supply voltage is referred to in the art as “Vmin”.
In modern SRAMs constructed with sub-micron feature sizes, the measure of Vmin will vary from cell to cell within an array, and therefore within the same multiple-array or multiple-block integrated circuit. This cell-to-cell variation stems from such known effects as random dopant fluctuation (“RDP”), line-end roughness (“LER”), and the like, which introduce observable variations among populations of transistors in the deep sub-micron regime. As a result, the Vmin for a particular memory will be determined by the cell within that memory with the poorest (i.e., highest) Vmin measurement.
It has been observed that Vmin tends to degrade over operating life in conventional CMOS SRAMs. An important mechanism in this regard is negative bias temperature instability (“NBTI”), which appears as an increase in threshold voltage over operating time. NBTI degradation affects primarily p-channel MOS transistors in modern CMOS integrated circuits, and adversely affects memory cell Vmin. Conventional manufacturing test flows for sub-micron CMOS SRAMs now commonly includes a “guardband” voltage to the power supply voltage during one or more functional tests. This reduced power supply voltage screens out (or invokes replacement via redundant rows or columns) those devices with a Vmin that is close to the pass/fail threshold at manufacture, within a margin corresponding to the expected NBTI drift over the desired operating life.
Another recently observed effect in deep sub-micron transistors is referred to in the art as “Random Telegraph Noise” (“RTN”). Physical defects within the gate dielectric of MOS transistors can trap charge during device operation, typically in response to bias on the transistor; other bias conditions or thermal effects can later “de-trap” or release that trapped charge. The trapping and de-trapping of charge via this mechanism is essentially a random process over time (mimicking the “dots” and “dashes” of a telegraph signal, as reflected in the common name of this mechanism). This trapping and de-trapping mechanism has an electrical effect of modulating the threshold voltage of the transistor. With the extremely small feature sizes and extremely thin gate dielectrics in modern MOS transistors, the trapping and de-trapping of even a single charge within the gate dielectric is reflected by variations in the transistor threshold voltage of as much as 10 to 20 mV. This mechanism can also cause fluctuations in the gate leakage of the transistor, with or without noticeable threshold voltage modulation.
In the SRAM context, the effects of RTN are observed as erratic changes in Vmin of memory cells over time, specifically with the affected bit failing a Vmin threshold due to a write failure, a cell stability failure during read cycles (or during a “dummy” read for half-selected cells in a write cycle), a data retention failure, or a data read failure (e.g., inadequate read current). A memory cell exhibiting such erratic failures over time is commonly referred to in the art as an unstable bit. Repeated testing of such an unstable bit with the same functional test pattern will fail a particular Vmin threshold at random times and pass at other times, with the random failures due to any of the above causes (write failure, stability failure, retention failure, data read failure) depending on the particular transistor parameters in that cell and on the bias and operational environment. This random behavior in repeated testing is described in Agostinelli et al., “Erratic Fluctuation of SRAM Cache Vmin at the 90 nm Process Technology Node”, Technical Digest of the International Electron Devices Meeting (IEEE, 2005), pp. 671-674, in which the probability distribution of Vmin fluctuation is described as depending on the number of observations, with the tail of the Vmin range distribution increasing with the number of observations.
The combination of RTN gate leakage or threshold shift, with the time-dependent threshold shift of NBTI, increases the possible threshold voltage shift in an SRAM over time. This necessitates an even larger guardband on the Vmin test at manufacture, in order to screen out those devices that may fail over time due to NBTI shift and that may experience the additional Vmin degradation from temporarily trapped charge due to RTN, essentially by increasing the test to a safer Vmin level. While this increased guardband will generally be effective to remove those devices subject to both NBTI and RTN, it is believed that such a severe guardband will also remove devices that, while having a Vmin close to but passing the NBTI-only guardband, will not exhibit RTN threshold shift, and would thus be reliable over the expected system life. Especially as feature sizes continue to shrink with advances in technology, the financial impact of yield loss from these “false failures” will become even more significant.
Similar memory cell failures due to the combination of RTN threshold shift with the time-dependent threshold shift of NBTI have also been observed in other memory cell types, including read-only memories (electrically programmable or mask programmable). Of course, some forms of read-only memories cannot be “written” with a false data state; in those cases, upsets due to RTN threshold shift and time-dependent threshold shift of NBTI manifest in these memories as read failures, in which the read data state applied to bit lines differs from the state persistently stored in the memory cell.